1. Field of the Invention
The present invention relates to non-volatile magnetic circuits, and in particular, to non-volatile memory, including latches.
2. Problems in the Art
A significant problem with RAM (random access memory) is that the memory is lost upon loss of power. This is contrary to ROM (read only memory) where data is typically stored during manufacturing and is non-volatile. Random access memory is utilized by a computer for fast storage of in-use programs or data.
Non-volatile memory, besides magnetic disks and tapes, is not new in the art. Computer core memory itself was non-volatile before the introduction of semi-conductor RAM in the early 1970""s. It was assembled from magnetic cores, which were fabricated out of magnetic ferrite materials. These transformer coils were tiny toroidal rings, which were threaded with fine copper wires. Current pulses through the wires would magnetize the cores either at a right or left handed direction to store a 0 or a 1; and thus have a bipolar or binary memory element. Each core was a bit. However, this memory was slow and expensive and was low density by today""s standards.
In comparison, present semi-conductor RAM is relatively fast, relatively cheap to fabricate in large quantities, and relatively small in size. However, it is volatile. Similarly, most semi-conductor digital components, such as latches, counters, flip-flops, etc. have the above-mentioned advantages, yet are also volatile. There is a need for non-volatile components of this type. Regardless of non-volatility, there is room in the art with respect to RAM or other digital logic components that are further reduced in size, speedier, more reliable, and can be operated by and consume less power.
Attempts have been made to return to the utilization of magnetism (non-volatile) as a method of storing binary information. An example of a magneto-resistive storage device is experimentation with anisotropic magnetoresistance (AMR) using one or more layers of AMR magnetic film. Localized portions of the material are magnetized in different directions to store the binary information.
Another example is the Giant Magneto-Resistive (GMR) effect. It results in larger changes in resistance in response to small magnetic fields in certain layered materials than are typically observed with the AMR effect. The GMR effect and a general explanation thereof are discussed in Prinz, Gary A., xe2x80x9cMagnetoelectronics,xe2x80x9d incorporated by reference herein. Depending on the magnetism relative to spin polarization of current, the GMR material can be more or less conductive for electrons of specific spin polarization.
It has been shown that the magnetic field generated by even small currents could thus xe2x80x9cprogramxe2x80x9d a GMR component to several xe2x80x9clogic statesxe2x80x9d, i.e. higher resistance or lower resistance. Thus, it is possible to xe2x80x9csensexe2x80x9d the logic state by sending current through the programmed GMR component and deriving its resistance (i.e. whether it is the higher or lower resistance). This produces a bipolar memory element that has the advantages of low power read or write, non-volatility, and self-containment. Also, importantly, there are no limitations to the number of read/write cycles known and both reading and writing can be done at high speeds; higher than most existing non-volatile latches or memory elements.
Spin-polarized tunneling or spin dependant tunneling (SDT) is discussed at Bobo, J. F., et al., xe2x80x9cSpin Dependent Tunneling Junctions with hard magnetic layer pinningxe2x80x9d, J. App. Phys. 83, 6685 (1998), which is herein incorporated by reference. In memory applications, SDT devices may be preferable to GMR devices in that they typically have a larger signal and higher intrinsic resistance for small area components.
However, the mere fact that SDT magneto-resistive storage devices have been pointed out as possible memory elements is not sufficient for effective implementation and operation in an actual circuit, where not only must data be stored in the device but also efficiently retrieved with a minimum of sensing circuitry. To perform adequately, the memory element must not only be programmable or writeable to at least two states, the different states must be reliably readable by the system. Further, it is important that the memory element be able to reliably withstand multiple, and preferably unlimited, read and/or write cycles.
There have been some attempts to create non-volatile, solid state latches or memory elements that improve over the state of the art. Many of such components require significant write energy. They have limitations regarding read/write speed and number of read/write cycles.
One specific example is called NOVRAM (from Xicor). It is relatively large in size and therefore is less conducive to large scale RAM and the like. It requires an off-chip component. It is also relatively slow.
It is therefore a primary object of the present invention to improve over the problems and deficiencies in the art.
Another object of the present invention is to provide random access memory that can maintain a state or store data without power, and is non-volatile.
Further objects, features, and advantages of the present invention include an apparatus and method for a non-volatile magnetic latch, which has:
a) low write energy and low program/reprogram energy;
b) higher read/write speed;
c) an unlimited number of read/write cycles;
d) the entire latch function included on-chip, and therefore no off-chip components are needed; and
e) small signal analysis to predict state of latch.
These and other objects, features, and advantages of the invention will become more apparent with further reference to the specification.
The invention is a non-volatile latch with magnetic based data storage that can be programmed using an on-chip current generated magnetic field. The latch relies on SDT component, as the fundamental data storage unit.
Resistance of the SDT component can be programmed to higher or lower values, for example, with an on-chip current generated field. This higher or lower resistance can then be sensed by a regenerative sequence, which senses an electrical potential imbalance, in one example, generated by SDT magneto-resistive storage devices with complimentary resistance. During regeneration, such an imbalance can be amplified and the latch will reach a logic high or logic low state.